Imec's Zsolt Tokei and Arm's Mohamed Awad outline CMOS 2.0, a next-generation architecture that pushes scaling beyond chiplets by partitioning circuits across stacked, specialized layers. The approach reframes Moore's Law continuation around 3D backside-power, hybrid bonding and design-technology co-optimization rather than pure transistor shrinks, with implications for advanced foundry, EDA and packaging roadmaps.
Why it matters: Forward-looking architecture discussion from Imec and Arm executives signals direction for advanced foundry, packaging and EDA roadmaps but carries no near-term earnings or capex catalyst.
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