Shipped vs Announced — The Vera Customer List Landed Before Venice's Launch Date — Research Note | Silicon Nexus
Research Notes· Jul 12, 2026· NVDA· 4 min read
Shipped vs Announced — The Vera Customer List Landed Before Venice's Launch Date
This week's CPU story wasn't about core counts. It was about five named customers.
Three CPU stories overlapped in one week
Between July 6–11, 2026, three CPU narratives ran in parallel. AMD locked its Zen 6 EPYC "Venice" launch to July 22, previewing up to 256 cores (Guru3D). Intel quietly raised prices across its Xeon lineup (Tom's Hardware). And Nvidia — the outsider in the CPU market — delivered Vera CPU systems to OpenAI, Anthropic, Oracle, and SpaceX (Yahoo Finance). Perplexity added its name to the list (The Motley Fool). That makes five named top-tier AI customers on one CPU platform in a single week.
Venice, by contrast, will arrive on July 22 with zero named hyperscaler commitments on the record. Intel's price hike is a monetization story on an installed base, not a new-socket story. This week the CPU narrative wasn't decided by core counts. It was decided by five names.
The gap between announced and shipped
Wedbush called Vera's 88-core architecture a genuine challenge to x86 (Wedbush note), and Morgan Stanley raised Nvidia's PT to $288 on Vera Rubin momentum. What the market underweighted is that these are not forward claims about "future x86 pressure."
The inference workloads of five top AI labs are already running on that socket.
That matters for three reasons.
First, it repositions AMD's July 22 launch. Venice ceases to be a counter-punch and becomes a claw-back — trying to reverse decisions already made. Oracle is arguably still in play. Anthropic, OpenAI, and SpaceX get progressively harder as kernel drivers, orchestration, and MoE routing kernels harden into a 12–18 month switching-cost moat.
Second, Nvidia's declaration that it is entering the $200B x86 CPU market (TechInAsia) is not a 2028 aspiration. This week's deliveries are the down payment. The Rosa CPU on TSMC 2nm/A16 is the roadmap continuation, not a discrete event.
Third, Intel's price increase clarifies which side of the confidence/defense line it sits on. New sockets are flowing to Nvidia and AMD; Intel has to extract margin from the remaining refresh base. Wells Fargo's AMD PT lift to $615 reflects the AMD-takes-Intel scenario, not an Intel holds its base one.
The memory backdrop: DDR5 at $47.8
DDR5 16Gb spot printed at $47.8 on July 12, 2026. That is the price context in which Vera systems are being racked, Meta's Iris custom chip enters September production, and Apple commits $30B to Broadcom. Every named Vera deployment is a fixed memory-per-rack floor, and DDR5 spot hasn't fully absorbed that floor yet. The tighter the shipping cadence, the further behind spot pricing lags installed capacity.
Risk: what could break the pattern on July 22
The narrative reverses only if AMD's Venice launch pries loose one of the named five. OpenAI or Anthropic publicly declaring a dual-vendor stance would be the strongest counter. But this week's list is delivered, not evaluating. Even a dual-vendor announcement takes at least two quarters to reverse deployed clusters.
Three things to watch: (1) how many named hyperscaler commitments AMD produces on July 22 alongside the Venice core-count reveal; (2) when Nvidia confirms Rosa's process node — TSMC 2nm vs A16 — as an execution signal; (3) whether Intel's post-hike unit shipment guidance holds or erodes on the next print.
The key data point this week is not that Vera exists. It is that five customers no longer need convincing. That is the specific input the Venice launch has to overcome twelve days from now.