The PM1763 Signal — Samsung's Nvidia Vera Rubin Storage Slot, and the Second AI Memory Vector the Market Isn't Pricing

The PM view — a second engine hiding behind the Q2 surprise

Samsung's Q2 operating profit of KRW 89.4 trillion — a roughly 18x year-on-year print — was framed almost entirely as an HBM4 story (TheElec, 2026-07-06). A quieter announcement in the same week deserves equal weight. Samsung began mass production of the PM1763, a PCIe 6.0 enterprise SSD designed into Nvidia's Vera Rubin platform — the generation after Blackwell (TheElec, 2026-07-08). Bandwidth doubles versus the prior PM1753.

Why this matters. Vera Rubin is the datacenter GPU standard from 2027 onward. Being designed in at the storage layer for that generation means Samsung has locked a NAND revenue pipe running from 2027 into 2029 — independent of the HBM4 print that made this quarter. For years the market has treated Samsung's NAND business as the weak link, and Michael Burry's short thesis leans heavily on commodity NAND pricing and inventory. The PM1763 ramp inverts that frame.

What the HBM-only lens missed

AI memory debate has been overwhelmingly HBM-centric. Intel disclosed XBM patents as an eventual HBM4 alternative. Micron is spending ~KRW 14T on a Hiroshima HBM fab. SK Hynix is raising $32B in US markets. All that capital is chasing HBM.

Meanwhile, the storage layer of AI workloads is a much quieter room. As LLM inference scales, KV cache offload, model parameter paging, and vector-DB backends drive rapid demand for PCIe 6.0-class low-latency, high-bandwidth eSSDs. Vera Rubin is the first hardware generation to bake that architecture in at the platform level. Samsung slid into that slot.

Why Samsung — the capacity asymmetry

Samsung's position in NAND is arguably stronger than in HBM. It owns the world's largest NAND capacity and is the only supplier that can absorb AI-server custom stacks at volume. Where SK Hynix has led on HBM, Samsung is now countering on AI eSSD.

The decision to defer CXL 3.1 (CMM-D 3.0) mass production to 2027 (TheElec, 2026-07-06) reads through the same lens. Intel's Diamond Rapids and AMD's EPYC Venice CPU delays kill near-term CXL 3.1 demand. Redirecting engineering and clean-room resources into the lines that actually monetize — HBM4 and PM1763 — is disciplined capital allocation, not weakness.