The Designer's Letter — The Week MediaTek's COO-Signed Notice Reclaimed Pricing Power for Taiwan's IC Designers
Subscription pivot, DDR2 +110%, ASP +30% — the cascade finally reached the design layer
The Designer's Letter
On June 22, MediaTek (2454-TW) COO Joe Chen sent customers a formally signed letter notifying them of across-the-board price hikes. This was not routine negotiation. The letter cited component shortages, capacity constraints, extended supplier lead times, and rising material and labor costs — a written commitment to pass-through. The next session MediaTek surged to limit-up and Taiwan's IC design ETF 00947 hit a record. Aspeed (5274) climbed toward NT$19,880, within reach of the NT$20,000 milestone.
The letter matters because for eighteen months Taiwan's fabless designers absorbed memory squeezes quietly. Every DRAM tightening compressed margins because cost pass-through ran a quarter or two late. A COO-signed notice published mid-cycle is the public declaration that the lag is over. JP Morgan's same-day note projecting AI ASIC shipments to grow at a 32% CAGR through 2028 — versus 7% for high-end GPUs — framed the broader rerating: pricing power is migrating from the foundry-memory layer toward the designers who own the architecture.
ASUS's Subscription Pivot — When +30% ASPs Broke the Purchase Model
The same week, ASUS (2357-TW) formally launched its Service Plus laptop subscription in Taiwan, with subscription volume up nearly 70% YoY. Management disclosed that notebook ASPs have risen ~30% since Q4 2025 and guided for another ~5% rise in H2 2026 — a cumulative 36.5% hike the PC industry hasn't seen in a generation. Once price increases breach the 30% threshold, lump-sum purchase economics break down for a meaningful share of buyers. That is the structural reason ASUS launched a subscription.
Along the same pressure line, Apple's Tim Cook told the WSJ this week that iPhone price hikes are "nearly unavoidable" because AI demand is bidding up the same DRAM/NAND supply, and Qualcomm is reportedly preparing a Snapdragon X2 refresh (Kalambo/Mahua/Glymur) instead of launching X3. The memory squeeze didn't only raise BOM costs — it is rewriting product cycle timing and the way consumers own PCs.
The DDR2 Tail — Mature Nodes Joined the Rally
TrendForce projects DDR2 contract prices will rise 35-40% in Q3 on top of Q2's 55-60% jump, putting the cumulative hike at roughly 110-120% YTD. Consumer-DRAM buyers downgrading to older, cheaper nodes pulled the squeeze all the way down to DDR2 — a node nobody had repriced in a decade. The cascade originates at TSMC. Same-day reporting indicates TSMC trimmed 28nm monthly wafer starts from ~200K at the start of 2026 to ~150K in June, redirecting the freed capacity to CoWoS silicon interposers. 28nm is no longer a consumer SoC node — it is the substrate layer for AI packaging infrastructure. UMC (2303) and Vanguard (5347) are absorbing the spillover, and UMC hit limit-up after a report alleging a 12nm/3nm tie-up with Intel at Arizona Fab 52. With DDR5 16Gb spot anchored at $46.5, the cascade keeps moving down the stack.
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