Google's Icefish TPU splits compute (TSMC) and I/O (Samsung 2nm). It's not proof the 72% share is breaking — it's proof the share holds even after customers have run out of room to put their wafers inside it.
This week was a paradox. TSMC printed a record 72% top-10 foundry share for Q1 2026 ($47.95B record industry revenue, +3.7% QoQ — TrendForce), broke ground on a Pingtung semiconductor supply-chain park with President Lai Ching-te personally pledging water, power and land, and watched foreign investors yank NT$10.99B out of 2330 in a single ex-dividend session — the sixth straight session of net selling, NT$35.7B in aggregate. In the same news cycle, The Information confirmed that Google's next-generation 'Icefish' TPU — co-designed with MediaTek, targeted for 2028 mass production — would split-manufacture across two foundries: TSMC for the compute die, Samsung's 2nm for the I/O chiplet.
Read at face value this is a packaging story. Read structurally, it is the first time in this AI cycle that a major TPU class has been deliberately bisected to qualify a second leading-edge node — a chip that would have run end-to-end at TSMC one cycle ago.
The bisection didn't happen alone
The same week, Cnyes analyst Gu Yu argued explicitly that TSMC's three-year lead in advanced nodes is intact, but its overflowing capacity is forcing customers like Apple, AMD and Nvidia to keep Samsung and Intel as backup options. Intel Foundry signed a multi-year DTCO (design technology co-optimization) agreement with Cadence to accelerate 14A's time-to-market — the kind of pact that only matters if customers actually plan to use the node. BofA double-upgraded Intel from Underperform to Buy with a $135 price target, citing 'CPU and foundry outlook' — the foundry word doing real work in that thesis for the first time in eighteen months.
This is not a TSMC-loses-share story. Q1 share rose to 72%, top-10 foundry revenue hit a record, CoWoS is so tight that overflow is creating a second-tier OSAT cycle in Taiwan (panel-level fan-out at 310x310mm entering as a parallel route), and Pingtung just broke ground. It is a story about a visible ceiling — and visible ceilings change customer behavior years before they bind.
Where the capex print starts to matter
CEO Score reported that in 2025 Samsung Electronics led global semis with 89.9T KRW (~$65B) in combined capex (52.2T) and R&D (37.7T), beating TSMC's 69.4T by more than 20T KRW. SK Hynix's chairman 최태원 told Nikkei the company will double wafer capacity within five years and triple it by 2034, with Japan flagged as the next overseas fab candidate. SEMI's WWSEMS report shows Q1 2026 global semiconductor equipment sales hit a record $36.55B (+14% YoY); Taiwan's May machinery exports printed a record $3.5B (+44% in electronics equipment).
The world is buying tools. But the tools take 18-24 months to install and qualify, meaning the capacity TSMC's customers want in 2026 had to be ordered in 2024 — and TSMC's allocated 2026-2028 wafers are simply the wafers it has. The capacity ceiling isn't a strategic choice. It's the literal tool count. Samsung's foundry, written off through 2024 as a node-quality story, has spent its way into a position where Google felt comfortable single-sourcing a 2nm I/O chiplet on it. That qualification didn't happen because Samsung suddenly became TSMC's equal. It happened because TSMC's allocated wafers in 2027 and 2028 are already gone.
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